Technique for increasing endurance of integrated circuit memory

ABSTRACT

A method increases endurance of an array of memory cells which have an endurance specified according to the number of change cycles that the memory cell can endure within a performance tolerance. The method is based on arranging the array into a plurality of sectors, and assigning a subset of addresses for storage of data structure expected to change a number of times that is sufficient to exceed the specified endurance of the memory cell in the array. A record is maintained indicating one of the plurality of sectors as a current sector, directing accesses using the subset of addresses to the current sector, counting changes executed to memory cells identified by the subset of addresses for the current sector, and changing the current sector to another one of the plurality of sectors when the count of changes exceeds the threshold.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of integrated circuit memorydevices, such as flash memory, and more particularly to memory devicesin which the memory array has an endurance specified according to anumber of program and erase cycles that the memory cell can endurewithin a performance tolerance, and for utilizing the memory array for agreater number of cycles than that specified.

2. Description of Related Art

Integrated circuit memory devices are typically used in computer systemsor other data processing systems in which there is a subset of data thatis changed more often than other data stored in the memory. For example,in data processing systems which rely on sensors to provide input data,the data structure in which the sensor data is stored is updated withnew sensor data more often than instructions for programs. Thus, thosesubsets of the memory which are used to store data structures thatchange often tend to fail due to the effects of the large number ofchange cycles that they endure.

Some integrated circuit memory architectures, such as flash memory basedon floating gate memory cells, have a relatively low endurance comparedto other technologies. However, the flash memory provides a non-volatilememory store which is necessary for some environments. The use of flashmemory in environments requiring high endurance memory is limited by thenative endurance of the memory cells on the device.

Thus, there is a need for a technique to allow utilization of anon-volatile memory devices in high change cycle environments.

SUMMARY OF THE INVENTION

The present invention provides a method for increasing endurance of anarray of memory cells which have an endurance specified according to thenumber of change cycles that the memory cell can endure within aperformance tolerance. For example, for an array of flash memorydevices, floating gate memory cells in the flash memory device have anendurance specified of for example 10,000 program/erase cycles that thememory cell can safely endure. Beyond the specified number, the celldegrades, and suffers charge gain or loss caused by damage to the tunneloxide in the cell or other damage of the memory cell.

The method is based on arranging the array into a plurality of sectors,and assigning a subset of addresses for storage of data expected tochange a number of times that is sufficient to exceed the specifiedendurance of the memory cell in the array. According to the method, arecord is maintained indicating one of the plurality of sectors as acurrent sector, directing accesses using the subset of addresses to thecurrent sector, counting changes executed to memory cells identified bythe subset of addresses for the current sector, and changing the currentsector to another one of the plurality of sectors when the count ofchanges exceeds the threshold. In this way, a data structure that mustbe updated many times can be stored in a non-volatile memory devicehaving limited endurance, by taking advantage of the areas in the memoryarray which store data that is not subject to as many change cycles.

Thus, according to one aspect the plurality of sectors include aparticular sector and a number N, where N is at least 1, of substitutesector(s) in the array. The step of changing the current sector includeschanging the current sector to one of the particular sector and the Nsubstitute sector(s). The number N is greater than 1, and preferablygreater than 5, and for an endurance cycling of 10 times the specifiedendurance, the number N is greater than or equal to 9.

According to another aspect, the method includes generating a count oferase operations to the current sector, and storing the count in anon-volatile memory store.

According to another aspect of the invention, the array is divided intoa first sector, a second sector and a third sector. Other embodimentsutilize more than three sectors. Addresses for accessing the arrayinclude a first subset of addresses normally assigned to the firstsector, a second subset of addresses normally assigned to the secondsector, and a third subset of that of addresses normally assigned to thethird sector. In this embodiment, the first subset of addresses isassigned to the data structure which is expected to undergo a largenumber of change cycles. The process of changing the current sectoraccording to this aspect of the invention includes directing accessesusing the first subset of addresses to the current sector, accessesusing the second subset of addresses to another one of the first, secondand third sectors, and accesses using the third subset of addresses to aremaining one of the first, second and third sectors. The current sectoris changed to another one of the first, second and third sectors whenthe count of changes exceeds the threshold. The changing of the currentsector includes selecting a next current sector, transferring datastored in the next current sector to the current sector, and redirectingaccesses using the first subset of addresses to the next current sector.Furthermore, the method includes redirecting accesses using the one ofthe second and third subsets of addresses that had been assigned to thenext current sector to the current sector, and updating the record ofthe current sector to indicate the next current sector. When more thanthree sectors are utilized, the current sector is cycled through morethan three sectors, for even greater endurance.

The present invention can also be characterized as an integrated circuitmemory including an array of floating gate memory cells, in which memorycells have an endurance specified according to a number of erase cyclesthat the memory cell can endure within a performance tolerance. Thearray includes a particular sector and a number N of substitute sectorsin the array. Addressing logic is coupled to the array which enablesaccess to memory cells in the array in response to addresses in a rangeof addresses. The range of addresses includes a subset of addresses foraccessing the particular sector in the array. The substitute sectorsfall outside the normal range of addresses. Erase cycling logic iscoupled to the addressing logic and the array, and maintains a recordindicating one of the particular sector and the N substitute sectors asthe current sector. The logic directs accesses using the subset ofaddresses to the current sector, counts the erases executed to memorycells identified by the subset of addresses for the current sector, andchanges the current sector another one of the substitute sectors and theparticular sector when the count of erases exceeds the threshold.

According to another aspect of the invention it can be characterized asintegrated circuit memory in which the addressing logic enables accessto memory cells in the array in response to addresses in a range ofaddresses that includes a first subset of addresses for accessing afirst sector in the plurality of sectors, a second subset of addressesfor accessing a second sector in the plurality of sectors, and a thirdsubset of addresses for accessing a third sector in the plurality ofsectors. Erase cycling logic is coupled to the addressing logic and tothe array, which maintains a record indicating one of the first, secondand third sectors is a current sector. The logic directs accesses usingthe first subset of addresses to the current sector, accesses using thesecond subset of addresses to another one of the first, second and thirdsectors and accesses using the third subset of addresses to a remainingone of the first, second and third sectors. The logic also countschanges executed in the memory cells identified by the first subset ofaddresses for the current sector and changes the current sector toanother one of the first, second and third sectors when the count ofchanges exceeds a threshold.

The erase cycling logic which changes the current sector includes logicto select a next current sector to which accesses using one of thesecond and third subset of addresses are directed, transfers data storedin the next current sector to the current sector, signals the addressinglogic to redirect accesses using the first subset of addresses to thenext current sector, signals the addressing logic to redirect accessesusing one of the second and third subsets of addresses to the currentsector, and updates the record of the current sector to indicate thenext current sector. Furthermore, the erase cycling logic includes logicwhich writes data from the current sector to the next current sectorprior to signaling the addressing logic to redirect accesses. Asmentioned before, more than three sectors can be cycled in this way forgreater endurance.

Accordingly, using for example a flash memory technology specified foran endurance of 10,000 program/erase cycles, an endurance of for example100,000 programs/erase cycles can be achieved for data structures havinghigh change expectations according to the present invention. The presentinvention provides techniques which solve the problem with a tradeoff ofpenalty in die size and/or the time consumed in the program and erasecycling.

Other aspects and advantages of the present invention can be seen uponreview of the figures, the detailed description and the claims whichfollow.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a simplified block diagram of an integrated circuit memorydevice according to a first embodiment of the present invention.

FIG. 2 is a diagram utilized for illustrating the process of controllingaccess to the memory array of FIG. 1.

FIG. 3 is a simplified diagram of an integrated circuit memory deviceaccording to a second embodiment of the present invention.

FIG. 4 is a diagram used in illustrating the process of controllingaccess to the memory array for the system of FIG. 3.

DETAILED DESCRIPTION

A detailed description of the present invention is provided with respectto FIGS. 1-4, in which FIGS. 1 and 3 illustrate alternativeimplementations of the present invention.

FIG. 1 illustrates an integrated circuit memory device comprising anarray 10 of flash memory cells. The array is implemented in one examplesuch as described in U.S. Pat. No. 5,526,307 entitled FLASH EPROMINTEGRATED CIRCUIT ARCHITECTURE invented by Yiu, et al. The integratedcircuit includes supporting circuitry including address inputs 11coupled to address buffer and latch 12. The address buffer and latch 12supplies address signals on line 13 to a wordline decoder 14, and abitline decoder 15, referred to as the X decoder and Y decoderrespectively. The Y decoder 15 is coupled to Y-pass gates 16 by whichthe bitlines are connected and disconnected to sense amplifiers 17 andprogram data high voltage circuits 18 used during program cycles. Theprogram data high voltage circuits 18 are coupled to a program datalatch 19 which receives data from input/output buffer 20. The senseamplifiers 17 are also coupled to the input/output buffer 20. The dataI/O pins 21 are coupled to I/O buffer 20. The I/O buffer 20 is alsoconnected to a command controller 22 which controls a write statemachine 23. Other control logic for the erase and program cycling isprovided in block 24. Control signal inputs for the output enable, chipenable and write enable signals are supplied on lines 25, 26 and 27respectively. Control logic 24 controls the address buffer and latch,and the write state machine 23. Also, the write state machine 23controls program and erase high voltage circuitry 28 which is coupled tothe flash memory array 10, and to the wordline drivers 14.

According to the present invention, an erase cycle recorder 29 isprovided which includes non-volatile memory cells for storing a count oferase cycles and for indicating a current sector. In this embodiment ofthe present invention, the flash memory array includes a plurality ofsectors, including a particular sector referred to as substitute sectorzero 30. N substitute sectors, referred to as substitute sectors 1-N arealso included on array. Each of the substitute sectors 1-N includes thesame number or a greater number of memory cells as the particularsector, sector 30. Additional logic including a wordline control logic31, and X decoder for the substitute array 32 is provided on the chip.The wordline controller 31 and X decoder for the substitute array arecontrolled by the erase cycle recorder 29 as indicated on line 33 andthe address buffer and latch 12 as indicated on line 13.

The memory is configured so that the particular sector, sector 30, fallswithin a particular subset of addresses for the flash memory array 10.The substitute sectors 1-N fall outside the normal address range.However, the X decoder for the substitute array is controllable by thewordline control logic 31 and the erase cycle recorder 33 to redirectaccesses within the address range of the particular sector 30 to acurrent sector selected from sectors 0, that is the particular sector30, through sector N.

This process can be logically understood with reference to FIG. 2, inwhich the flash memory array is represented by block 100. Block 100includes six sectors, sectors A-F in this example. A small sector,sector 0 in this example corresponds to the particular sector 30 of FIG.1. The substitute sectors for sector C include sectors C1-C10 in theexample. Thus, accesses to the subset of addresses, ADDR C, whichcorrespond to the sector C in the array 100 are directed to a currentsector selected from the particular sector, sector C, and one of the Nsubstitute sectors, sectors C1-C10. As a particular number of erasecycles occurs to the address range, the logic switches the currentsector from sector C to the first sector in the substitute sector. Afterthe particular number of erases happens to the first substitute sector,the logic switches to the second substitute sector and so on cyclingthrough the substitute sectors and the particular sector.

In this way, the endurance of the memory array for the data structurestored in the sector C is multiplied by the number of good substitutesectors utilized in the cycling process. Thus for example, the erasecycling recorder includes a non-volatile register. The erase cyclingrecorder records every X cycles of changes to the data structure storedin the address range for the particular sector 30. For example, every 16cycles, every 128 cycles, or every 1K erase cycles could be utilized asa counting interval. In one alternative, every erase cycle is counted inthe erase cycle recorder, so that if the power off/on events occuroften, erase cycles are not missed. In this alternative, everysubstitute sector O-N is coupled with a counter comprising non-volatilecells, to ensure that the cells in the counter do not exceed the cyclingspecification. For flash memory, a write operation includes an erasefollowed by a program. So counting erases works to count all changecycles on a cell.

The current substitute array is disabled and the next substitute arrayis enabled when the erase cycling recorder reaches the threshold. Theerase cycling recorder 29 is controlled by the write state machine 23.The write state machine 23 activates the non-volatile register in theerase cycling recorder at the end of the last erase cycle within theinterval, that is for example at the end of the 16th, 128th or 1024therase, so that the controller recognizes the time to disable one andenable another subarray during the access.

Accordingly, in order to achieve 100,000 cycles or more, for a specificsector based on technology constrained to 10,000 cycles on a given cell,a substitute array is provided that is transparent to the user. Thesubstitute array is divided into ten equal sectors, each sector having asize equal to the particular sector 30 in the main array. In someapplications, for example, the sectors A, B, D, E and F are provided forfixed code storage or for other data structures which are not changedfrequently. Sector C, however, is provided for a data structure whichmay require updating up to 100,000 times.

The sector C may be part of the main array such as illustrated in FIG.1, or alternatively, included in the set of substitute sectors,independent of the main array, depending on the particular choice ofimplementation.

In alternative systems, one or more of the substitute sectors C1-C10 canalso be treated as a redundant sector for sector C. If sector C has adefect, then one of the sectors C1-C10 can be used to replace sector C.If C does not have a defect, the substitute sectors are used forextended endurance purposes as mentioned above. Also, sectors C1-C10must be good sectors in order to achieve the more than 100,000program/erase cycling in this example. Otherwise, the endurance islimited to the native endurance of the device, such as 10,000 cyclestimes the number of good substitute sectors on the device.

FIGS. 3 and 4 illustrate an alternative implementation of the presentinvention, in which a trade off in extended program/erase cycling timeis utilized to prevent the die size penalty of the example of FIG. 1.According to the implementation of FIG. 3, an integrated circuit memoryis provided with an array 200. As in FIG. 1, addresses are supplied onlines 201 to an address buffer and latch 202. The address buffer andlatch 202 supplies address signals on line 203 to an X decoder 204 whichincludes logical addressing according to this implementation of thepresent invention, and to a Y decoder 205. The Y decoder is coupled topass gates 206 for the bitlines. Pass gates connect bitlines in thearray 200 to sense amplifiers 207, and to the program data high voltagecircuits 208. The program data high voltage circuits 208 are coupled toa program data latch 209 which is in turn connected to input/output I/Obuffers 210. Also the sense amplifiers 207 are coupled to the I/Obuffers 210. Input and output data are provided on line 211. The I/Obuffer 210 is also coupled to a command control block 212 whichinterprets commands received at the I/O buffer 210. The command controlblock 212 is coupled to the write state machine 213. The write statemachine 213 in turn is coupled with control logic 214 for the erase andprogram cycling which receives the output enable, chip enable and writeenable signals on lines 215, 216 and 217 respectively. Also the writestate machine 213 controls the program and erase high voltage circuits218 which are coupled to the array and to the wordline drivers in the Xdecoder 204. Furthermore, according to the present invention the writestate machine is coupled to an erase cycle recorder 219. The erase cyclerecorder 219 is coupled to the X decoder 204 to control the logicaladdressing to implement the endurance cycling of the present invention.The process of managing endurance cycling according to this embodimentcan be understood with reference to FIG. 4. According to this example,the array includes a plurality of sectors, sectors 0-N as illustrated inthe figure. In this example, three of the sectors are utilized. Thus,sectors 1, 2 and 3 can be utilized to improve erase cycling endurancefor a particular data structure. In FIG. 4, a first erase process on thedata structure D is illustrated where the data structure is stored inthe sector 1, 300, other data A is stored in the second sector 301, andyet other data B is stored in a third sector 302. The erase cyclerecorder controls the logical addressing in the X decoder 204 to executethe process which involves first erasing the physical sector in whichthe data structure D is stored to generate a physical sector having anerased data structure, ED as indicated at 303. Next, the data from Afrom the physical sector 301 is copied to the physical sector 300 asindicated at 304. Finally, the physical sector which had stored data Ais erased, and the logical addressing is updated so that the physicalsector 301 corresponds to the erased data structure D as indicated at305. Finally, the data structure D is restored to the physical sector305.

On the next erase or after X erase cycles recorded by erase cyclerecorder 219 on the data structure D, data A is stored in the firstsector 300, the data structure D is stored in the second sector 301, andthe data B is stored in the third sector 302. The process first erasesthe sector storing the data structure D is indicated at 306. Next, thedata B from the third sector 302 is copied to the physical sector havingthe erased data structure as indicated at 307. Lastly, the third sector302 is designated the sector for storing the data structure D asindicated at 308.

On a next erase cycle or after X erase cycles recorded by erase cyclerecorder 219 for the data structure D, the data A is stored in the firstsector 300, the data B is stored in the second sector 301, and the datastructure D is stored in the third sector 302. First, the third sectoris erased as indicated at 309 to provide an erased physical sector. Thedata A from the first sector is copied to the third sector as indicatedat 310. Finally, the first sector is erased and designated as thephysical sector for the data structure D as indicated at 311.

Following this cycling technique, the effective endurance of the memoryarray for storing a data structure D is increased, by taking advantageof the relatively low erase cycling which occurs in the data A and B.

Accordingly, this alternative implementation achieves the same purposewith a tradeoff that involves extended erase time in order to hide theswap with dynamic addressing algorithm explained above with respect toFIGS. 3 and 4. This algorithm utilizes the rarely used program/eraselife of other sectors in the array to distribute the wear of the targetsector that requires the extended cycling. The penalties of thisapproach are extended erase time, and overhead of dynamic addressing inorder to apply the correct addressing to the current sector.

Accordingly, the present invention provides an integrated circuit memorydevice including an array of memory cells that have a native endurance.However, techniques are provided for storing a data structure in thedevice which can be changed more times than the native endurance allows,by using substitute sectors, and/or logical addressing schemes to takeadvantage of the relatively low cycling endured by other sectors in thearray.

The foregoing description of a preferred embodiment of the invention hasbeen presented for purposes of illustration and description. It is notintended to be exhaustive or to limit the invention to the precise formsdisclosed. Obviously, many modifications and variations will be apparentto practitioners skilled in this art. It is intended that the scope ofthe invention be defined by the following claims and their equivalents.

What is claimed is:
 1. A method for increasing endurance of an array ofmemory cells, the memory cells in the array having an endurancespecified according to a number of change cycles that the memory cellcan endure within a performance tolerance, comprising: arranging thearray into a plurality of sectors; assigning a subset of addresses forstorage of data expected to change a number of times sufficient toexceed the specified endurance of the memory cells in the array; andmaintaining a record indicating one of the plurality of sectors as acurrent sector, directing accesses using the subset of addresses to thecurrent sector, counting changes executed to memory cells identified bythe subset of addresses for the current sector, and changing the currentsector to another one of the plurality of sectors when the count ofchanges exceeds a threshold.
 2. The method of claim 1, wherein theplurality of sectors include a particular sector and a number N, where Nis at least one, of substitute sector(s) in the array, the changing thecurrent sector includes changing the current sector to one of theparticular sector and the N substitute sector(s).
 3. The method of claim2, wherein the number N is greater than
 1. 4. The method of claim 2,wherein the number N is greater than
 5. 5. The method of claim 2,wherein the number N is greater than or equal to
 9. 6. The method ofclaim 1, wherein the memory cells in the array comprise floating gatememory cells.
 7. The method of claim 6, wherein the change cyclescomprise an erase of the current sector followed by a program of thecurrent sector.
 8. The method of claim 7, including generating a countof erase operations to the current sector, and storing the count in anon-volatile store.
 9. The method of claim 1, wherein the step ofmaintaining a count includes providing a plurality of non-volatilestores, the plurality of non-volatile stores being coupled withrespective sectors in the plurality of sectors, and storing the countfor the current sector in the non-volatile store coupled with thecurrent sector.
 10. The method of claim 1, wherein addresses foraccessing the array include a first subset of addresses for accessing afirst sector in the plurality of sectors, a second subset of addressesfor accessing a second sector in the plurality of sectors, and a thirdsubset of addresses for accessing a third sector in the plurality ofsectors; and wherein the assigned subset of addresses is first subset ofaddresses, and wherein the record indicates one of the first, second andthird sectors as the current sector, and the changing of the currentsector includes directing accesses using the first subset of addressesto the current sector, accesses using the second subset of addresses toanother one of the first, second and third sectors and accesses usingthe third subset of addresses to a remaining one of the first, secondand third sectors, and changing the current sector to another one of thefirst, second and third sectors when the count of changes exceeds athreshold.
 11. The method of claim 10, wherein the changing of thecurrent sector includes selecting a next current sector, transferringdata stored in the next current sector to the current sector, andredirecting accesses to using the first subset of addresses to the nextcurrent sector.
 12. The method of claim 10, wherein the changing of thecurrent sector includes selecting a next current sector to whichaccesses using one of the second and third subset of addresses aredirected, transferring data stored in the next current sector to thecurrent sector, redirecting accesses to using the first subset ofaddresses to the next current sector, redirecting accesses using the oneof the second and third subsets of addresses to the current sector, andupdating the record of the current sector to indicate the next currentsector.
 13. An integrated circuit memory, comprising: an array offloating gate memory cells, the memory cells in the array having anendurance specified according to a number of change cycles that thememory cell can endure within a performance tolerance; the arrayincluding a particular sector and a number N, where N is at least one,of substitute sector(s) in the array, the substitute sector(s) includinga number of memory cells equal to or greater than the number of cells inthe particular sector in the array; addressing logic, coupled to thearray, which enables access to memory cells in the array in response toaddresses in a range of addresses, and wherein the range of addressesincludes a subset of addresses for accessing the particular sector ofthe array; and array cycling logic, coupled to the addressing logic andthe array, which maintains a record indicating one of the particularsector and the N substitute sector(s) as a current sector, directsaccesses using the subset of addresses to the current sector, countschanges executed to memory cells identified by the subset of addressesfor the current sector, and changes the current sector to another one ofthe substitute sector(s) and the particular sector when the count oferases exceeds a threshold.
 14. The integrated circuit memory of claim13, wherein the number N is greater than
 1. 15. The integrated circuitmemory of claim 13, wherein the number N is greater than
 5. 16. Theintegrated circuit memory of claim 13, wherein the number N is greaterthan or equal to
 9. 17. The integrated circuit memory of claim 13,wherein change cycles to the array comprise an erase of the accessedsector followed by a program of the accessed sector, and the eraseoperation in the write cycles is counted by the array cycling logic asan erase cycle.
 18. The integrated circuit memory of claim 13, whereinthe array cycling logic includes logic which generates a count of eraseoperations to the current sector, and stores the count in a non-volatilestore.
 19. The integrated circuit memory of claim 17, wherein thenon-volatile store comprises a non-volatile memory on the integratedcircuit.
 20. The integrated circuit memory of claim 13, including aplurality of non-volatile stores coupled with respective sectors in theplurality of sectors, and wherein the array cycling logic includes logicwhich generates a count of erase operations to the current sector, andstores the count in the non-volatile store coupled with the currentsector.
 21. An integrated circuit memory, comprising: an array offloating gate memory cells, the memory cells in the array having anendurance specified according to a number of change cycles that thememory cell can endure within a performance tolerance, the arrayincluding a plurality of sectors; addressing logic, coupled to thearray, which enables access to memory cells in the array in response toaddresses in a range of addresses, and wherein the range of addressesincludes a first subset of addresses for accessing a first sector in theplurality of sectors, a second subset of addresses for accessing asecond sector in the plurality of sectors, and a third subset ofaddresses for accessing a third sector in the plurality of sectors; andarray cycling logic, coupled to the addressing logic and the array,which maintains a record indicating one of the first, second and thirdsectors as a current sector, directs accesses using the first subset ofaddresses to the current sector, accesses using the second subset ofaddresses to another one of the first, second and third sectors andaccesses using the third subset of addresses to a remaining one of thefirst, second and third sectors, counts changes executed to memory cellsidentified by the first subset of addresses for the current sector, andchanges the current sector to another one of the first, second and thirdsectors when the count of changes exceeds a threshold.
 22. Theintegrated circuit memory of claim 21, wherein the array cycling logicwhich changes the current sector includes logic to select a next currentsector, transfer data stored in the next current sector to the currentsector, and signal the addressing logic to redirect accesses to usingthe first subset of addresses to the next current sector.
 23. Theintegrated circuit memory of claim 21, wherein the array cycling logicwhich changes the current sector includes logic to select a next currentsector to which accesses using one of the second and third subset ofaddresses are directed, transfer data stored in the next current sectorto the current sector, signal the addressing logic to redirect accessesto using the first subset of addresses to the next current sector,signal the addressing logic to redirect accesses using the one of thesecond and third subsets of addresses to the current sector, and updatethe record of the current sector to indicate the next current sector.24. The integrated circuit memory of claim 23, wherein the array cyclinglogic which changes the current sector includes logic to erase the nextcurrent sector prior to signaling the addressing logic to redirectaccesses.
 25. The integrated circuit memory of claim 21, wherein changecycles comprise an erase of the accessed sector followed by a program ofthe accessed sector, and the array cycling logic counts the eraseoperation within a change cycle as a change cycle.
 26. The integratedcircuit memory of claim 21, wherein the array cycling logic includeslogic which generates a count of change operations to the currentsector, and stores the count in a non-volatile store.
 27. The integratedcircuit memory of claim 26, wherein the non-volatile store comprises anon-volatile memory on the integrated circuit.
 28. The integratedcircuit memory of claim 21, including a plurality of non-volatile storescoupled with respective sectors in the plurality of sectors, and whereinthe array cycling logic includes logic which generates a count of eraseoperations to the current sector, and stores the count in thenon-volatile store coupled with the current sector.